1. Field of the Invention
This invention relates to computer processor architecture, and more particularly to a system and method for marking registers during speculative execution to distinguish between usable data and unusable data.
2. Background
Historically, computer processors executed instructions one at a time in the order presented to the processor. As processors have advanced, the concepts of pipelining, looking ahead, out of order processing, and speculative execution have been incorporated in many of the more popular computer processors, including those used in personal computers. These techniques allow a computer processor to execute independent instructions while waiting for other high latency instructions to produce their result. The ability to continue to execute instructions and use execution resources while waiting for a high latency instruction is important in achieving high performance in current day processors. Although advancements in processor design have drastically improved the latency for typical processor instructions, the latency of instructions that must access memory have improved only slightly. For example, in some current day processors it may take 1000 times longer for the processor to execute a “load” involving a cache miss when compared to the time needed to process and “add”. This is because the cache miss requires the processor to retrieve needed data from memory to complete executing the load instruction.
As such, when implementing the performance increasing techniques mentioned above, when a cache miss occurs, the processor has a lot of time within which to do work. Some of the speculative execution performed by the processor creates data that is not accurate and must be deleted as unuseful. In this way, the processor may speculatively execute many instructions needlessly. For example, scratch mode execution may allow for execution based on branch predictions by allowing the processor to speculatively execute instructions following a cache miss. However, in many circumstances, the execution continues based on invalid data contained in the destination register of the load that missed the cache.
Invalid data produced by a cache miss may be propagated through multiple levels of instructions that are ultimately dependent on the invalid data. As such, the invalid data renders the results of these instructions or sequences of instructions generally useless. Therefore, execution of instructions that consume values resulting from cache misses may negatively impact the benefits achieved through speculative execution. Loads depending on invalid data offer no prefetching benefit and can cause translation look-aside buffer and/or cache pollution. In addition, branches depending on invalid data are often resolved incorrectly, steering scratch mode execution off of the branch path indicated by the branch predictor and/or rendering the results useless.